1. Field of the Invention
This invention relates to a process for producing multilayer wiring boards. More specifically, the invention relates to a process for producing multi-layer wiring boards of a "build-up" type having via holes or trench-like channels which have been formed by removing interlevel dielectric layers in selective areas to provide electrical interconnections of more than one level of conductor patterns.
2. Description of Relevant Art
With the recent advances electronic technology, efforts are being made to increase the degree of integration in electronic devices such as computers and to achieve faster calculating operations. Multilayer wiring boards are not an exception and those which permit high-density wiring or packaging are in demand; it is known that this requirement can be satisfied by multilayer wiring boards of the build-up type having via holes or trench-like channels for establishing an electrical connection between a first and a second level of conductor pattern.
Two typical examples of a an earlier technology multilayer wiring board fabricated by the build-up procedure are shown in FIGS. 6 and 7. A substrate 21 is overlaid with a first level of conductor pattern 22 which, in turn, is provided with a photosensitive resin layer (interlevel dielectric layer) 23 that is formed by screening or otherwise patterning an electrically insulating ceramic paste composition; the interlevel dielectric layer 23 is exposed by photolithography, developed and selectively etched away to form via holes 25; thereafter, electro- or non electroplating is performed to provide a conductive layer 26 within each via hole 25 or as a coextensive mass that fills each via hole 25 and the interlevel dielectric layer 23; subsequently, a second level of conductor pattern (not shown) is formed such that it is electrically connected to the underlying first level of conductor pattern 22.
The multilayer wiring boards fabricated by this earlier technology method have several problems. First, high-definition boards of sufficiently small feature sizes are not attainable if the interlevel dielectric layer is made of ceramic materials. Secondly, if the light-sensitive resin layer is employed, via holes will be formed that either have a rectangular cross section with vertical sidewalls (see FIG. 6) or tend to experience side etching by the liquid developer used in photolithography (see FIG. 7). In either case, the throwing power of the electro- or nonelectroplating technique employed to provide the conductor layer 26 within the via holes 25 or over the interlevel dielectric layer 23 is not satisfactory (no uniform plate is deposited) as shown in FIGS. 6 and 7 (see the encircled area A) and conduction failure will sometimes occur. This problem could be dealt with by sufficiently increasing the amount of electroless plate deposit to prevent shortcircuiting but, on the other hand, the weight of the substrate will increase unavoidably, making it difficult to produce high-density, high-definition multilayer wiring boards.
With a view to forming a multilayer wiring board of high reliability using a smaller amount of electroless plate deposit, it has been proposed that resin particles soluble in an oxidizer be contained in a photosensitive resin layer slightly soluble in the oxidizer, with the resin particles being dissolved out by the action of the oxidizer, whereupon the interlevel dielectric layer is roughened to provide better adhesion to a conductive layer. This technology may be found in Unexamined Published Japanese Patent Application (kokai) No. 215623/1994. In this patent, strong acids such as chromic acid are used as the oxidizer in the roughening of the surface of the interlevel dielectric layer, but this is not preferred on account of the adverse effects that will be caused on the operating personnel and the substrate.
Recent environmental considerations require photosensitive resins that permit the use of dilute aqueous alkali solutions as the liquid developer and Unexamined Published Japanese Patent Application (kokai) No. 196856/1994 has proposed a photosensitive resin that is rendered developable with a dilute aqueous alkali solution by introducing carboxyl groups. However, the so modified light-sensitive resin is prone to suffer a decrease in insulation resistance and that resistance, with occasional shorts. Hence, it has been difficult to realize multi-layer wiring boards of high reliability by the proposed method. In addition, if an interlevel dielectric layer is made of this modified light-sensitive resin, it cannot withstand heating to temperatures higher than about 140.degree. C. and it is also difficult to realize high peeling strength; therefore, if the interlevel dielectric layer made of this light-sensitive resin is used in modern versions of high-density wiring boards, problems such as flaking and chipping often occur due to damage of the interlevel dielectric layer.
Another approach that has been proposed is to make an interlevel dielectric layer of a thermosettable heat-resistant epoxy resin blended with an inorganic filler and then form via holes by means of a high-power laser such as a CO.sub.2 gas laser or an excimer laser. However, in addition to the high equipment cost, the via holes formed have a rectangular cross section and conduction failure may occasionally occur even if a conductor layer is provided within each via hole; as a further problem, the sidewalls of the via holes are so smooth that the required adhesion to the applied conducive layer is not achieved.